Senior Test Development Engineer
Test Engineer 4 Responsibilities: Own all TE activities for assigned NPI programs from first silicon through mass production release — including test program development, characterization, and NPI flow execution Work closely with R&D, Product Engineering, and Operations teams to drive NPI milestones through Final Production Release Develop and optimize ATE test programs and hardware for production and characterization testing — primarily on the S100 platform Design and execute device characterization plans; collect parametric data across process, voltage, and temperature corners to establish test limits and validate test coverage Develop T-FMEA for all new NPI programs; identify and document test coverage gaps with full datasheet spec traceability before production release Define and implement new test strategies to improve coverage, reduce test time, and improve test hardware architecture for high-volume production Implement CP1 functional screening and CP2 full parametric flows including analog trim sequences; coordinate FT trim sequence validation against design team specifications Create probe and final test schematics and lead or participate in hardware review meetings; lead probe card and FT fixture bring-up at OSAT from NPI through mass production Port and correlate test programs across alternate OSAT platforms; document correlation approach, site-to-site GR&R & Cpk sign-off criteria, and qualification lot results Support OTP programming qualification and post-program verify flows; provide first-response ATE technical support for production issues at primary and alternate OSATs Identify and drive test time and test cost reductions; document best practices and sustaining procedures for long-term program health Minimum Qualifications: Bachelor’s degree in Electrical, Electronic, Computer Engineering (or equivalent) 5+ years of experience in ATE test engineering within the semiconductor industry Direct ATE test program development from NPI through mass production on the S100 platform; sustaining-only backgrounds will not meet this requirement Ability to interpret hardware schematics, datasheet parameters, and DFT documents Strong understanding of analog/mixed-signal test methodology, including trim, characterization, and parametric screening Experience designing multi-site test architectures: DUT board design, contact schemes, site-to-site correlation, and parallel test efficiency Hands-on probe card and FT fixture bring-up experience Excellent problem-solving skills and attention to detail; must be a team player Strong written and verbal communication skills; proficiency in English required; Mandarin working proficiency preferred Desired Qualifications Direct experience with MEMS force/capacitive sensing or haptic actuator ATE test Expertise in S100 tester platform — test program development and debugging tools; Advantest V93000 (SMT7/SMT8) experience is a plus Experience in automotive testing for haptic feedback or force-sensing applications is a plus Experience with OTP programming on ATE: charge pump control, VPP sourcing, and post-program retention verification Prior work on T-FMEA development and coverage gap analysis of inherited test programs Experience with alternate OSAT qualification: correlation lot design, Cpk sign-off, and multi-site validation Demonstrated ability to define and implement new test strategies that reduce hardware complexity or test time Experience with PCB schematic and layout tools (OrCAD or equivalent) Proficiency in scripting or programming for test automation: C/C++, Python, or Java Knowledge of DFT, DFM, and 6-sigma principles #LI-Onsite Apply To This Job